-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
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-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "02/22/2016 00:06:29"
                                                            
-- Vhdl Test Bench template for design  :  TIME_TOP
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY TIME_TOP_vhd_tst IS
END TIME_TOP_vhd_tst;
ARCHITECTURE TIME_TOP_arch OF TIME_TOP_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL i_sys_clk : STD_LOGIC;
SIGNAL i_sys_rst : STD_LOGIC;
SIGNAL o_min0_display : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL o_min1_display : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL o_sec0_display : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL o_sec1_display : STD_LOGIC_VECTOR(6 DOWNTO 0);
COMPONENT TIMER_TOP
	PORT (
	i_sys_clk : IN STD_LOGIC;
	i_sys_rst : IN STD_LOGIC;
	o_min0_display : BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0);
	o_min1_display : BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0);
	o_sec0_display : BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0);
	o_sec1_display : BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END COMPONENT;
BEGIN
	i1 : TIMER_TOP
	PORT MAP (
-- list connections between master ports and signals
	i_sys_clk => i_sys_clk,
	i_sys_rst => i_sys_rst,
	o_min0_display => o_min0_display,
	o_min1_display => o_min1_display,
	o_sec0_display => o_sec0_display,
	o_sec1_display => o_sec1_display
	);
clk: PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
	  i_sys_clk<='1';    
     wait for 10ns;    
     i_sys_clk<='0';    
     wait for 10ns;                    
--WAIT;                                                       
END PROCESS ;                                           
tb : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
    
	 i_sys_rst <= '0';
	 wait for 100ns;
	 i_sys_rst <= '1';
	 wait for 10ns;
	 -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS ;                                                           
END TIME_TOP_arch;
